Internal Data Memory Organization
Figure 2–6. Data Memory Controller Interconnect to Other Blocks (TMS320C6701)
Block 1
(32K bytes)
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
2-14
'C6701CPU
Side B
32
64
16
16
16
16
Data memory controller
16
(DMEMC)
16
16
16
32
Peripheral
External
bus
memory
controller
interface
Side A
64
32
Block 0
(32K bytes)
16
16
16
16
16
16
16
16
32
32
DMA
controller
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0