Texas Instruments TMS320C6201 Reference Manual page 338

Data Transmission and Reception
11-20
McBSP reset: When the receiver and transmitter reset bits, RRST and
XRST, are written with 0, the respective portions of the McBSP are reset and
activity in the corresponding section stops. All input-only pins, such as DR
and CLKS, and all other pins that are configured as inputs are in a known
state. FS(R/X) is driven to its inactive state (same as its polarity bit,
FS(R/X)P) if it is an output. If CLK(R/X) are programmed as outputs, they
are driven by CLKG, provided that GRST = 1. The DX pin is in the high-im-
pedance state when the transmitter is reset. During normal operation, the
sample rate generator can be reset by writing a 0 to GRST. GRST should
be low only when neither the transmitter nor the receiver is using the sample
rate generator. In this case, the internal sample rate generator clock CLKG,
and its frame sync signal (FSG) is driven inactive (low). When the sample
rate generator is not in the reset state (GRST = 1), FSR and FSX are in an
inactive state when RRST = 0 and XRST = 0, respectively, even if they are
outputs driven by FSG. This ensures that when only one portion of the
McBSP is in reset, the other portion can continue operation when FRST
= 1 and frame sync is driven by FSG.
Sample-rate generator reset: As mentioned previously, the sample rate
generator is reset when the device is reset or when its reset bit, GRST, is
written with 0. In the case of device reset, the CLKG signal is driven by a
divide-by-2 internal clock source and FSG is driven inactive (low). The in-
ternal clock source for the 'C6211/C6711 is CPU clock, while the internal
clock source for 'C6211/C6711 is CPU/2 clock (half of the CPU clock fre-
quency). If you want to reset the sample rate generator when neither the
transmitter nor receiver is fed by the CLKG and FSG, you can program
GRST in the SRGR to 0. CLKG and FSG are driven inactive (low). When
GRST = 1, CLKG runs as programmed in the SRGR. If FRST = 1, FSG
is driven active (high) after eight cycles have elapsed.
The serial port initialization procedure is as follows:
1) Set XRST = RRST = FRST = 0 in SPCR. If the device has been reset, this
step is not required.
2) Program only the McBSP configuration registers, not the data registers,
that are listed in Table 11–2, as required when the serial port is in the reset
state (XRST = RRST = FRST = 0).
3) Wait two bit clocks to ensure proper internal synchronization.
4) Set up data acquisition as desired.
5) Set XRST = RRST = 1 to enable the serial port. The value written to the
SPCR should have only the reset bits changed to 1 and the remaining bit
fields should have the same value as in step 2.
6) Set FRST = 1. If it is the frame master, the McBSP is now ready to transmit
and/or receive.