Table of Contents
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transmit with data overwrite 11-45
triggering a power–down 14-4
TRST signal 15-2, 15-5, 15-6, 15-11, 15-16, 15-24
TSTAT parameters 12-10
two level memory architecture 4-1
two–dimensional (2D) transfers 6-20
two–dimensional destination or source
transfer 6-14
two–dimensional transfer, definition 6-5
two–dimensional transfers 6-22
types of EDMA transfers 6-20
U
unexpected frame sync pulses 11-37
unexpected transit frame sync 11-47
unsynchronized transfers 6-7
unused RAM 6-9
user–accessible peripherals 1-8
V
VelociTIt advanced VLIW architecture 1-1
very long instruction word (VLIW) 1-1
W
wait/data phase (Tw/Td) 8-36
wake up from a power down 14-4
word aligned 8-10
word count register 4-8
word index 4-9
write hold 9-12
write hold and read hold bit fields 9-13
write hold fields 9-14
write interface 8-15
write miss 4-9
write strobe 9-12
write transfer 5-2
X
XARB bit value 8-44
XBD register 8-7
XBEA register 8-6, 8-7
XBHC register 8-6, 8-7
XBHC register descriptions 8-25
XBIMA register 8-6, 8-7
XBISA register 8-7
XCE space control registers 8-9
XCE spaces 8-3
XCE0 Space Control Register 8-6
XCE1 Space Control Register 8-6
XCE2 Space Control Register 8-6
XCE3 Space Control Register 8-6
XCNTL signal 8-7
XDS510 emulator, JTAG cable. See emulation
XEVT0 6-18
XEVT1 6-18
XSREMPTY bit 11-8
Index
Index-19
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