Texas Instruments TMS320C6201 Reference Manual page 247

Figure 9–1. External Memory Interface in the TMS320C6201/C6202/C6701BlockDiagram
Figure 9–2. External Memory Interface in the TMS320C6211/C6711BlockDiagram
Timers
Interrupt selector
McBSPs
HPI control
DMA control
EMIF control
Host port
PLL
Power
down
Boot
configuration
External
memory
interface
(EMIF)
Multichannel
buffered
serial port 1
Enhanced
(McBSP 1)
DMA
controller
Multichannel
buffered
serial port 0
(McBSP 0)
Host port
interface
(HPI)
Power down logic
TMS320C6000
Peripheral
bus
controller
DMA
controller
EMIF
Instruction fetch
Instruction dispatch
L2 memory
Instruction decode
4 banks
64K bytes
Data path 1
A register file
L1 S1 M1 D1
Timer 1 Timer 0
External Memory Interface
Data memory
Data memory
controller
CPU core
Program fetch
Instruction dispatch
Instruction decode
Data path Data path
1 2
Program memory controller
Program memory/cache
L1P cache
direct mapped
4K bytes
CPU core
Control
registers
In–circuit
emulation
Data path 2
B register file
D2 M2 S2 L2
L1D cache
2–way set
associative
4K bytes
Overview
9-3