Texas Instruments TMS320C6201 Reference Manual page 451

Of the following two cases, the worst-case path delay is calculated to deter-
mine the maximum system test clock frequency.
Case 1: Single processor, direct connection, DTMS/DTDO timed from TCK low.
t
pd TCK–DTMS
t
pd TCK–DTDI
In this case, the TCK-to-DTMS/DTDL path is the limiting factor.
Case 2: Single/multiprocessor, DTMS/DTDO/TCK buffered input, DTDI buffered out-
put, DTMS/DTDO timed from TCK low.
t
pd (TCK–TDMS)
t
pd (TCK–DTDI)
In this case, the TCK-to-DTDI path is the limiting factor.
t t
d DTMSmax d DTCKHmin
+
t
TCKfactor
[31ns 2ns 10ns]
+
0.4
+ 107.5ns (9.3 MHz)
t t
d TTDO d DTCKLmax
+
t
TCKfactor
[15ns 16ns 7ns]
+
0.4
+ 9.5ns (10.5 MHz)
t t
d (DTMSmax) DTCKHmin
+
[31ns 2ns 10ns
+
0.4
+ 110.9ns (9.0 MHz)
t t
d (TTDO)
d DTCKLmax
+
[15ns
15ns 7ns
+
0.4
+ 120ns (8.3 MHz)
Designing for JTAG Emulation
Emulation Design Considerations
t
su TTMS
t
su DTDLmin
t
su (TTMS)
t
TCKfactor
1.35ns]
t
su (DTDLmin
)
t
TCKfactor
10ns]
t
(bufskew)
t
d (bufskew)
15-17