L1D Address Allocation - Texas Instruments TMS320C6201 Reference Manual

4.4 L1D Description
Figure 4–8. L1D Address Allocation
31
Tag
The L1D is organized as a 64 set 2–way set associative cache with a 32 byte
line size. The two least significant bits of a requested address are ignored by
the L1D since the smallest access size is for a word. The next bit of the address
is used to address the correct word. Bits four and three select one of the four
8 byte sublines in the addressed set. The next six bits select the set within the
cache that the addressed data maps to. The remaining bits of the address are
used as a unique tag for the requested data. Figure 4–8 illustrates how a 32
bit address is allocated to provide the word index, subline index, set index and
tag data for the L1D.
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A cache hit returns data to the CPU in a single cycle. Operation on a cache
miss depends on the direction of the access. On a read miss, the L1D sends
a read request to the L2 to fetch the data. When the data is returned from the
L2, the L1D analyzes the set that the addressed data maps to in each way.
The L1D controller stores the new data into the set that was least recently used
(LRU). If the data in that set has been modified but the corresponding address
has not be updated (the cache line is dirty), that data is written out to the L2.
In this way, cached data that has been modified will not be discarded before
it is updated in its original address. If two read misses occur in the same cycle,
they are serialized by the L1D so that only one request is presented to the L2
at a time. On a write miss, the L1D sends the write request to the L2. The data
is not stored in the L1D. Write requests from the L1D to the L2 are buffered.
If a write request is still pending from the L1D when a read miss occurs, this
buffer is allowed to empty before the read request is sent to the L2.
The L1D only operates as a cache and cannot be memory mapped. The L1D
does not support freeze or bypass modes. The only values allowed for the data
cache control (DCC) field in the CPU control and status register (CSR) are
000b and 010b. All other values for DCC are reserved, as shown in Table 4–5.
TMS320C6211/C6711 Two-Level Internal Memory
10 5
Set
L1D Description
4 3 2 1
Subline Word Offset
0
4-9