Texas Instruments TMS320C6201 Reference Manual page 468

Index
internal data RAM address mapping 3-7
internal master address register 8-6
internal memories 4-2
internal memory 1-6, 3-6, 4-3
internal memory and cache configurations available
on the current TMS320C6000 3-2
Internal Memory Block Diagram, figure 4-3
Internal Memory Control Register Fields,
figure 4-13
internal memory control registers 4-5
internal memory control registers addresses 4-5
internal peripheral bus interrupt selector
registers 10-6
internal program memory 1-9, 2-3, 8-4
modes 2-3
internal program RAM 3-4
internal program RAM address mapping 3-5
Internal Program RAM Address Mapping in Memory
Mapped Mode, table 3-4
internal program space 3-5, 3-6
internal transfer controller 7-5
interrupt
channel interrupt enable register (CIER) 6-32
channel interrupt pending register (CIPR) 6-32
configuring 13-10
default mapping 13-9
EDMA generation 6-32
EDMA servicing 6-34
EMIF SDRAM timer 6-18
external pin 6-18
host port host to DSP
multiplexer register 13-8
polarity register 13-7
registers 13-7
SDINT 9-17
signal timing 13-5
source between DSPINT and XFRCT
counter 8-25
sources 13-2
TCC to DMA mapping 6-33
timer 0 6-18
xBHC register field DSPINT 8-25
interrupt
EDMA transfer complete code 6-18
timer 1 6-18
interrupt enable register 6-32
Index-10
6-18
interrupt multiplexer high register diagram,
figure 13-8
interrupt multiplexer low register diagram,
figure 13-8
interrupt pending register 6-32
interrupt processing 6-6
Interrupt selector 1-8
interrupt selector 1-9
interrupt sources 1-12
interrupt the CPU 12-2
interrupts
CPU 11-22
DSPINT 7-18
timer 12-11
introduction iii to x, 1-1
TMS320 family overview 1-2
invalidating a block of data 4-8
invalidating a block of data in the L1D 4-12
invalidating data in the L1D 4-12
invalidation, L2 4-21
J
JTAG emulator
buffered signals 15-9
connection to target system 15-1 to 15-24
no signal buffering 15-8
pod interface 15-4
L
L1 program cache controller 4-3
L1D
2–way set associative cache diagram,
figure 4-11
address allocation, figure 4-9
data cache mode settings 4-10
description 4-9
flush word count register fields 4-12
L1D cache 4-2
L1D flush base address 4-5
L1D Flush Base Address Register Fields,
figure 4-12
L1DFBAR and L1DFWC registers 4-12
L1P
address allocation figure 4-6
description 4-6