Table of Contents
Advertisement
Expansion Bus Host Port Operation
8-34
The timing diagram shown in Figure 8–21 can be referenced for a visual
description of the steps involved in release of the expansion bus ownership as
initiated by the XBOFF signal. The diagram illustrates the backoff condition for
both internal bus arbiter enabled and internal bus arbiter disabled . The step
by step description of the events in Figure 8–21 follows:
1) The 'C6202 is expansion bus master and initiates address phase of a read
transaction. The XAS signal is active and valid address is presented.
2) The XRDY signal is high indicating that the external device is not ready to
perform the transaction. Also, the external device drives XHOLD active,
indicating a bus request.
3) The 'C6202 is still holding the expansion bus waiting for XRDY to become
low.
4) The external device asserts XBOFF, indicating a potential deadlock condi-
tion.
5) The DSP responds by releasing the expansion bus. When the internal bus
arbiter is enabled, the DSP asserts XHOLDA. When the internal bus arbi-
ter is disabled the DSP deasserts XHOLD. It can take a several clock
cycles before 'C6202 responds to XBOFF. Figure 8–21 shows the fastest
response time, one cycle.
6) The expansion bus ownership changes. The new master drives the ex-
pansion bus. XBOFF is deasserted.
7) The external device releases the bus after performing the desired transac-
tions.
8) The XHOLDA is removed, and the DSP resumes the expansion bus own-
ership.
9) The DSP performs a burst read of four words.
The DSP automatically tries to restart the transfer interrupted by a backoff from
the point where the interruption took place. The transfer restart is completely
transparent to the user.
Advertisement
Chapters
Table of Contents
