Texas Instruments TMS320C6201 Reference Manual page 359

Tms320c6000 series peripherals
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11.3.7 Serial Port Exception Conditions
11.3.7.1 Reception With Overrun: RFULL
There are five serial port events that can constitute a system error:
Receive overrun (RFULL = 1)
Unexpected receive frame synchronization (RSYNCERR = 1)
Transmit data overwrite
Transmit empty (XEMPTY = 0)
Unexpected transmit frame synchronization (XSYNCERR = 1)
RFULL = 1 in the SPCR indicates that the receiver has experienced overrun
and is in an error condition. RFULL is set when the following conditions are
met:
DRR has not been read since the last RBR-to-DRR transfer.
RBR is full and an RBR-to-DRR copy has not occurred.
RSR is full and an RSR-to-RBR transfer has not occurred.
The data arriving on DR is continuously shifted into RSR. Once a complete
element is shifted into RSR, an RSR-to-RBR transfer can occur only if an RBR-
to-DRR copy is complete. Therefore, if DRR has not been read by the CPU or
the DMA controller since the last RBR-to-DRR transfer (RRDY = 1), an RBR-
to-DRR copy does not take place until RRDY = 0. This prevents an RSR-to-
RBR copy. New data arriving on the DR pin is shifted into RSR, and the pre-
vious contents of RSR is lost. After the receiver starts running from reset, a
minimum of three elements must be received before RFULL can be set, be-
cause there was no last RBR-to-DRR transfer before the first element.
This data loss can be avoided if DRR is read no later than two and a half CLKR
cycles before the end of the third element (data C) in RSR, as shown in
Figure 11–25.
Either of the following events clears the RFULL bit to 0 and allows subsequent
transfers to be read properly:
Reading DRR
Resetting the receiver (RRST = 0) or the device
Another frame synchronization is required to restart the receiver.
Figure 11–24 shows the receive overrun condition. Because element A is not
read before the reception of element B is complete, B is not transferred to DRR
Data Transmission and Reception
Multichannel Buffered Serial Ports
11-41

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