Texas Instruments TMS320C6201 Reference Manual page 475

SPI Protocol: CLKSTP 11-80
SRC Address 6-12
SRC address parameter updates 6-30
SRC/DST Address 6-14
SRC/DST address updates 6-29
standard McBSP operation 11-33
stop operation 5-13
straight, unshrouded, 14-pin 15-3
subline index 4-9
SUM/DUM fields 6-28, 6-29
summary, TMS320C6211 boot configuration 10-5
summary of 'C6211 memory map 10-7
switching from one peripheral to the next 8-10
synchronization 5-17
frame (block) 6-19
frame phases 11-25
read/write 6-19
synchronization of EDMA transfers 6-17
synchronizing event 6-5
synchronous
interface 9-5
memory types 9-44
Synchronous burst SRAM (SBSRAM) 1-11
synchronous burst SRAMs (SBSRAMS) 9-43
Synchronous DRAM (SDRAM) 1-11
synchronous DRAM (SDRAM) 9-2
synchronous host port mode 8-26
synchronous master/slave interface 1-10
synchronous mode 8-5
synchronous–burst SRAM (SBSRAM) 9-2
T
T1 standards 1-11
tag data 4-9
tag RAM 4-7, 4-11
target cable 15-12
target system, connection to emulator 15-1 to
15-24
TCC value 6-33
TCINT bit 6-32
TCK signal 15-2, 15-3, 15-5, 15-6, 15-11, 15-16,
15-23
TDI signal 15-2, 15-3, 15-4, 15-5, 15-6, 15-7,
15-10, 15-11, 15-16, 15-17
TDM serial port control register (TSPC)
TXM bit 11-17, 11-55
XRDY bit 11-9
TDM serial port interface 11-78
TDO output 15-3
TDO signal 15-3, 15-4, 15-6, 15-7, 15-17, 15-23
test bus controller 15-20, 15-23
test clock 15-10
The Bus Master Reads a Burst of Data From the
'C6202, figure 8-39
The Expansion Bus Interface in the TMS320C6202
Block Diagram, figure 8-4
The Expansion Bus Master Writes a Burst of Data to
the 'C6202, figure 8-37
time events 12-2
timer 8-4
timer control register 12-4
timer control register field description, table 12-4
timer interrupt 6-18
timer operation in clock mode, figure 12-9
timer operation in pulse mode, figure 12-9
timers 1-8, 1-9
block diagram 12-3
clock source selection 12-8
counter register 12-6
counting 12-8
emulation operation 12-11
enabling counting 12-7
interrupts 12-11
overview 12-2
period register 12-6
pulse generation 12-9
register boundary conditions 12-11
registers 12-4
resetting 12-7
timing, requirements 9-34
timing calculations 15-6 to 15-7, 15-16 to 15-24
timing diagram, expansion bus master writes a burst
of data 8-37
Timing Diagrams for Asynchronous Host Port Mode
of the Expansion Bus, figure 8-43
Timing Diagrams for Bus Arbitration
XHOLD/XHOLDA (Internal bus arbiter is
disabled), figure 8-45
timing of external interrupt related signals,
figure 13-6
TINT0 6-18
Index
Index-17