Texas Instruments TMS320C6201 Reference Manual page 158

EDMA Interrupt Generation
6.13 EDMA Interrupt Generation
Figure 6–14. Channel Interrupt Pending Register (CIPR)
31
15 14 13
CIP15 CIP14 CIP13 CIP12
RW,+0 RW,+0 RW,+0 RW,+0
Figure 6–15. Channel Interrupt Enable Register (CIER)
31
15 14 13
CIE15 CIE14 CIE13 CIE12
RW,+0 RW,+0 RW,+0 RW,+0
6-32
The EDMA controller is responsible for generating channel-complete
interrupts to the CPU. Unlike the 'C6201 DMA controller which has individual
interrupts for each DMA channel, the EDMA generates a single interrupt
(EDMA_INT) to the CPU on behalf of all 16 channels. The various control reg-
isters and bit fields facilitate EDMA interrupt generation.
When TCINT bit in options entry is set to '1' for a EDMA channel and a specific
transfer complete code (TCC) is provided, the EDMA controller sets a bit in the
channel interrupt pending register (CIPR) shown in Figure 6–14. The CIPR bit
number that gets set is dictated by the TCC value programmed. Lastly, the im-
portant action is to generate the EDMA_INT to the CPU. To do this, the corre-
sponding interrupt enable bit should be set in the channel interrupt enable reg-
ister (CIER) shown in Figure 6–15.
Therefore for a channel completion event to generate an interrupt to the CPU,
the TCINT and the relevant CIER bit should be enabled. CIPR is equivalent
to an interrupt pending register whose sources are the transfer complete
codes and CIER is similar to an interrupt enable register. Note that if the CIER
bit is disabled, the channel completion event is still registered in the CIPR if its
TCINT=1. Once the CIER bit is enabled, the corresponding channel interrupt
is sent to the CPU. If the CPU interrupt (defaults to CPU_INT8) is enabled, its
ISR is executed.
12 11 10 9
CIP11 CIP10 CIP9
RW,+0 RW,+0 RW,+0
12 11 10 9
CIE11 CIE10 CIE9
RW,+0 RW,+0 RW,+0
Reserved
R, +0
8 7 6 5
CIP8 CIP7 CIP6 CIP5
RW,+0 RW,+0 RW,+0 RW,+0
Reserved
R, +0
8 7 6 5
CIE8 CIE7 CIE6 CIE5
RW,+0 RW,+0 RW,+0 RW,+0
4 3 2 1
CIP4 CIP3 CIP2 CIP1
RW,+0 RW,+0 RW,+0 RW,+0
4 3 2 1
CIE4 CIE3 CIE2 CIE1
RW,+0 RW,+0 RW,+0 RW,+0
16
0
CIP0
RW,+0
16
0
CIE0
RW,+0