Texas Instruments TMS320C6201 Reference Manual page 335

Table 11–7. Receive/Transmit Control Register (RCR/XCR) Field Descriptions (Continued)
Name Function
RDATDLY Receive data delay
RDATDLY = 00b: 0-bit data delay
RDATDLY = 01b: 1-bit data delay
RDATDLY = 10b: 2-bit data delay
RDATDLY = 11b: Reserved
XDATDLY Transmit data delay
XDATDLY = 00b: 0-bit data delay
XDATDLY = 01b: 1-bit data delay
XDATDLY = 10b: 2-bit data delay
XDATDLY = 11b: Reserved
RPHASE 2 Receive PHASE 2. Applicable only for dual-phase frames. Mainly used for I
feature. Applicable only for 'C6211/C6711 device.
RPHASE 2 = 0:
RPHASE 2 = 1:
This is applicable when frame syncs are inputs or outputs.
XPHASE 2 Transmit PHASE 2. Applicable only for dual-phase frames. Mainly used for I
feature. Applicable only for 'C6211/C6711 device.
XPHASE 2 = 0:
XPHASE 2 = 1:
This is applicable when frame syncs are inputs or outputs
RWDREVRS Receive 32-bit bit reversal feature. Applicable only for 'C6211/C6711 device.
RWDREVRS = 0: 32-bit reversal disabled
RWDREVRS = 1: 32-bit reversal enabled. 32-bit data is received LSB first.
XWDREVRS Transmit 32-bit bit reversal feature. Applicable only for 'C6211/C6711 device.
XWDREVRS = 0: 32-bit reversal disabled
XWDREVRS = 1: 32-bit reversal enabled. 32-bit data is transmitted LSB first.
The start of phase 2 is unaffected by receive frame sync.
The second phase in a dual-phase frame starts when the
receive frame sync transitions to the opposite edge that started
the first phase.
The start of phase 2 is unaffected by transmit frame sync.
The second phase in a dual-phase frame starts when the
transmit frame sync transitions to the opposite edge that
started the first phase.
RWDLEN should be set for 32-bit operation; else operation is
undefined.
XWDLEN should be set for 32-bit operation; else operation is
undefined.
McBSP Interface Signals and Registers
Multichannel Buffered Serial Ports
Section
11.3.4.7
11.3.4.7
2
S 11.3.4.3
2
S 11.3.4.3
11.3.9
11.3.9
11-17