Texas Instruments TMS320C6201 Reference Manual page 140

EDMA Transfer Parameters
Table 6–3. EDMA Channel Options Field Description (Continued)
6.6.2 SRC/DST Address
6-14
Field Description
TCINT Transfer complete interrupt
TCINT=0; Transfer complete indication disabled. CIPR
bits are not set upon completion of a transfer.
TCINT=1; The relevant CIPR bit is set on channel
transfer completion. The bit (position) set in the CIPR is
the TCC value specified.
2DD/2DS 2-dimensional destination or source transfer
2DD/2DS = 0; Not a 2-D transfer.
2DD/2DS = 1; 2-Dimensional transfer enabled.
DUM/SUM Destination / source (address) update mode
DUM/SUM = 00b; No address modification
DUM/SUM = 01b; Address increment depends on
2DD/2DS, and FS bit-fields
DUM/SUM = 10b; Address decrement depends on
2DD/2DS, and FS bit-fields
DUM/SUM = 11b; Address modified by the element
index/frame index depending on 2DD/2DS, and FS bits.
ESIZE Element size
ESIZE=00b; 32-bit word
ESIZE=01b; 16-bit half-word
ESIZE=10b; 8-bit byte
ESIZE=11b; reserved
PRI Priority levels for EDMA events
PRI=000b; Reserved; Urgent priority level reserved
ONLY for L2 requests. Not valid for EDMA transfer
requests.
PRI=001b; High priority EDMA transfer
PRI=010b; Low priority EDMA transfer
PRI=011b to 111b; reserved
The 32-bit source/destination address fields in the EDMA parameters speci-
fies the starting byte address of the source and destination. The src/dst ad-
dresses can be modified using the SUM/DUM field in the options parameter.
See details in section 6.12.
Section
6.13
6.8 and
6.12
6.12
6.10
6.14