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1.3 Features and Options of the TMS320C6000 Devices
The 'C6000 devices execute up to eight 32-bit instructions per cycle. The de-
vice's core CPU consists of 32 general-purpose registers of 32-bit-word length
and eight functional units:
Two multipliers
Six arithmetic logic units ( ALUs)
The 'C6000 generation has a complete set of optimized development tools,
including an efficient C compiler, an assembly optimizer for simplified assem-
bly-language programming and scheduling, and a Windows
ger interface for visibility of source code execution characteristics.
Features of the 'C6000 devices include:
Advanced VLIW CPU with eight functional units, including two multipliers
and six arithmetic units
J
Executes up to eight instructions per cycle for up to ten times the per-
formance of other DSPs
J
Allows designers to develop highly effective RISC-like code for rapid
development
Instruction packing
J
Gives code size equivalence for eight instructions executed serially or
in parallel
J
Reduces code size, program fetches, and power consumption
Conditional execution of all instructions
J
Reduces costly branching
J
Increases parallelism for higher sustained performance
Efficient code execution on independent functional units
J
Industry's most efficient C compiler on DSP benchmark suite
J
Industry's first assembly optimizer for fast development and improved
parallelism
Features and Options of the TMS320C6000 Devices
based debug-
Introduction
1-5
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