Texas Instruments TMS320C6201 Reference Manual page 102

Initiating a Block Transfer
5.4.1.1 DMA Channel Reload Registers
5-14
Repetitive operation: This operation is a special case of continuous opera-
tion. Once a block transfer finishes, the DMA controller repeats the previous
block transfer. In this case, the CPU does not preload the reload registers with
new values for each block transfer. Instead, the CPU loads the registers only
before the first block transfer.
Enabling autoinitialization: By writing START = 11b in the channel's primary
control register, you enable autoinitialization. In this case, after completion of
a block transfer, the selected DMA channel registers are reloaded and the
DMA channel is restarted . If you are restarting after a pause, START must be
rewritten as 11b for autoinitialization to be enabled.
For autoinitialization, the successive block transfers are assumed to be similar.
Thus, the reload values are selectable only for those registers that are modified
during a block transfer: the transfer counter and address registers. Thus, the
DMA channel transfer counter as well as the DMA channel source and destina-
tion address registers have associated reload registers, as selected by the asso-
ciated RELOAD fields in the DMA channel primary control register (see
Figure 5–2).
It is possible to not reload the source or destination address register in autoin-
itialization mode. This capability allows a register to maintain its value during
a block transfer. Thus, you do not have to dedicate a DMA global data register
to a value that was static during a block transfer. A single channel can use the
same value for multiple channel registers. For example, in split-channel mode,
the source and destination address can be the same. On the other hand, multi-
ple channels can use the same reload registers. For example, two channels
can have the same transfer count reload register.
Upon completion of a block transfer, the channel registers are reloaded with
the value from the associated reload register value. In the case of the DMA
channel transfer counter register, reload occurs after the end of each frame
transfer, not just after the end of the entire block transfer. The reload value for
the DMA channel transfer counter is necessary whenever multiframe transfers
are configured, not just when autoinitialization is enabled.
As discussed in section 5.11.2, the DMA controller can allow read transfers to
get ahead of write transfers, and it provides the necessary buffering to facilitate
this capability. To support this, the reload that's necessary at the end of blocks
and frames occurs independently for the read (source) and write (destination)
portions of the DMA channel. Similarly, in the case of split-channel operation de-
scribed in section 5.8, the source and destination addresses are independently
reloaded when the associated transmit or receive element transfers are com-
pleted.