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HPI Registers
7.3.3
Host Device Using DSPINT to Interrupt the CPU
7.3.4
CPU Using HINT to Interrupt the Host
7-18
1) The host polls the HPIC register for HRDY = 1.
2) The host writes the desired HPIA value. This step is skipped if HPIA is
already set to the desired value.
3) The host writes a 1 to the FETCH bit.
4) The host polls again for HRDY = 1.
5) The host performs an HPID read operation. In this case, the HPI is already
in the ready state (HRDY = 1).
6) If this was a read with postincrement, go to step 4. For a read from the
same location, go to step 3.For a read to a different address, go to step
2.
The HRDY bit can be used alone for write operations as follows:
1) The host polls for HRDY = 1.
2) The host writes the desired HPIA value. (This step is skipped if HPIA is
already set to the desired value.)
3) The host performs an HPID write operation. For another write operation,
go to step 1.
The host can interrupt the CPU by writing to the DSPINT bits in the HPIC. The
DSPINT bit is tied directly to the internal DSPINT signal. By writing
DSPINT = 1 when DSPINT = 0, the host causes a low-to-high transition on the
DSPINT signal. If you program the selection of the DSPINT interrupt with inter-
rupt selector, the transition of DSPINT is detected as an interrupt condition by
the CPU. The CPU can clear the DSPINT bits by writing a 1 to DSPINT. Neither
a host nor a CPU HPIC write with DSPINT = 0 affects the DSPINT bit or signal.
The CPU can send an active interrupt condition on the HINT signal by writing
to the HINT bit in the HPIC. The HINT bit is inverted and tied directly to the HINT
pin. The CPU can set HINT active by writing HINT = 1. The host can clear the
HINT to inactive by writing a 1 to HINT. Neither a host nor a CPU write to HPIC
with HINT = 0 affects either the HINT bit or the HINT signal.
The HINT bit is read twice on the host interface side. The first and second half-
word reads by the host can yield different data if the CPU changes the state of
this bit between the two read operations.
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