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5.6.2
Automated Event Clearing
5.6.3
Synchronization Control
The latched STAT for each synchronizing event is automatically cleared only
when any action associated with that event is completed. Events are cleared
as quickly as possible to reduce the minimum time between synchronizing
events. This capability effectively increases the rate at which events can be
recognized. This is described for each type of synchronization:
Clearing read synchronization condition: The latched condition for read
synchronization is cleared when the DMA completes the request for the
associated read transfer.
Clearing write synchronization condition: The latched condition for write
synchronization is cleared when the DMA completes the request for the
associated write transfer.
Clearing frame synchronization condition: Frame synchronization clears
the RSYNC STAT field when the DMA completes the request for the first
read transfer in the new frame.
The DMA of the 'C6202 allows for more flexible control over how external
synchronization events are recognized. The polarity of external events can be
inverted to an active-low by setting WSPOL and/or RSPOL to 1. WSPOL
affects write-synchronized transfers, while RSPOL affects read- and
frame-synchronized transfers.
During a frame-synchronized transfer, the DMA channel may be configured
(by setting FSIG = 1) to not recognize an external interrupt as a synchroniza-
tion event while performing a burst. The channel will internally monitor its burst
status, and will latch its synchronization event only when a frame transfer is
not in progress.
Synchronization: Triggering DMA Transfers
Direct Memory Access (DMA) Controller
5-19
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