Figure 6–2. EDMA Controller
The EDMA controller comprises:
Event and interrupt processing registers
Event encoder
Parameter RAM, and
Address generation hardware
A block diagram of the EDMA controller is shown in Figure 6–2.
EDMA parameter RAM
Channel 0 params
Channel 1 params
Channel 15 params
Reload channel 0
params
Reload channel 1
params
Reload channel 15
params
Unused
(scratch area)
Address
to EMIF/peripherals
Generation
FSM
Event
encoder
EDMA Controller
Overview
6-3