Read Transfer Initiated By The Tms320C6202 And Throttled By; Xwait And Xrdy (Internal Bus Arbiter Disabled) - Texas Instruments TMS320C6201 Reference Manual

Burst Read Transfer
Figure 8–19. Read Transfer Initiated by the TMS320C6202 and Throttled by

XWAIT and XRDY (Internal Bus Arbiter Disabled)

XCLKIN (input)
XHOLD (output)
XHOLDA (input)
XAS (output)
XW/R (output)
XBLAST (output)
XBE[3:0] (output)
XD[31:0] (i/o)
XRDY (input)
XWAIT (output)
The timing presented in Table 8–16 can be referenced for a visual description
of the steps required to complete a burst read initiated by the 'C6202 and
throttled by the XWAIT and XRDY signals.
1 2 3 4 5 6 7 8
AD
The step by step description of the events marked above the waveforms in
Figure 8–19 follows:
1) The 'C6202 requests the expansion bus by asserting XHOLD output.
2) The DSP waits for the expansion bus.
3) The external bus arbiter asserts the XHOLDA signal, and the 'C6202
starts driving the bus. The XAS, XW/R, XBLAST, XBE[3:0] signals
become outputs, and the XRDY signal becomes an input.
4) Address phase: During this phase, XAS is asserted and the address is
presented on the expansion bus.
9 10 11 12 13 14 15 16
BE
D1 D2 D3 D4
Expansion Bus Host Port Operation
17 18 19 20 21 22 23
D5 D6 D7 D8
Expansion Bus
24
8-29