Texas Instruments TMS320C6201 Reference Manual page 402

SPI Protocol: CLKSTP
11.7.1 McBSP Operation as the SPI Master
11-84
When the McBSP is the SPI master, it generates the master clock CLKX and
the slave enable FSX. Therefore, CLKX should be configured as an output
(CLKXM = 1) and FSX should be configured as an output that can be con-
nected to the slave enable (SS) input on the slave device (FSXM = 1). The
DXR-to-XSR transfer of each element generates the slave enable FSX.
Therefore, the FSGM field of the sample rate generator register (SRGR) must
be set to zero. The SPI protocol specifies that the slave needs to be enabled
before the transfer of the data. In other words, FSX needs to be asserted (low)
before the McBSP starts shifting out data on the DX pin. Refer to the MOSI and
FSX waveforms in Figure 11–54 and Figure 11–55. Therefore, XDATDLY
must be programmed to 1. When the McBSP is the SPI master, an XDATDLY
value of 0 or 2 causes undefined operation.
As the SPI master, the McBSP generates CLKX and FSX through the internal
sample rate generator. As discussed in section 11.5.2.1, the CLKSM bit in the
SRGR should be set to specify either the CPU clock or the external clock input
(CLKS) as the clock source to the internal sample rate generator. The
CLKGDV (clock divide ratio) in SRGR should be programmed to generate
CLKX at the required SPI data rate. The McBSP generates a continuous clock
(CLKX) internally and gates the clock off (stops the clock) to the external inter-
face when transfers are finished. The McBSP's receive clock is provided from
the internal continuously running clock, so the receiver and transmitter both
work internally as if clocks do not stop. Selection of the clock stop modes over-
rides the frame generator bit fields (FPER and FWID) of the the sample rate
generator register (SRGR).