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Figure 11–15. AC97 Bit Timing Near Frame Synchronization
CLKR
FSR
DR
P2E12B1
{
†
PxEyBz denotes phase x, element y, and bit z.
11.3.5 McBSP Standard Operation
1-bit data delay
P2E12B0
P1E1B15
During a serial transfer, there are typically periods of serial port inactivity
between packets or transfers. The receive and transmit frame synchronization
pulse occurs for every serial transfer. When the McBSP is not in the reset state
and has been configured for the desired operation, a serial transfer can be initi-
ated by programming (R/X)PHASE = 0 for a single-phase frame with the required
number of elements programmed in (R/X)FRLEN1. The number of elements can
range from 1 to 128 ((R/X)FRLEN1 = 00h to 7Fh). The required serial element
length is set in the (R/X)WDLEN1 field in the (R/X)CR. If a dual-phase frame is
required for the transfer, RPHASE = 1 and each (R/X)FRLEN(1/2) can be set to
any value between 00h and 7Fh.
Figure 11–16 shows a single-phase data frame of one 8-bit element. Since the
transfer is configured for a 1-bit data delay, the data on the DX and DR pins
are available one bit clock after FS(R/X) goes active. This figure as well as all
others in this section use the following assumptions:
(R/X)PHASE = 0, specifying a single-phase frame
(R/X)FRLEN1 = 0b, specifying one element per frame
(R/X)WDLEN1 = 000b, specifying eight bits per element
(R/X)FRLEN2 = (R/X)WDLEN2 = Value is ignored.
CLK(R/X)P = 0, specifying that the receive data is clocked on the falling
edge and that transmit data is clocked on the rising edge
FS(R/X)P = 0, specifying that active (high) frame sync signals are used
(R/X)DATDLY = 01b, specifying a 1-bit data delay
Data Transmission and Reception
{
P1E1B14
P1E1B13
Multichannel Buffered Serial Ports
P1E1B12
11-33
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