Texas Instruments TMS320C6201 Reference Manual page 476

Index
TINT1 6-18
TMS signal 15-2, 15-3, 15-4, 15-5, 15-6, 15-7,
15-10, 15-11, 15-15, 15-16, 15-17, 15-23
TMS/TDI inputs 15-3
TMS320 DSPs, applications, table 1-3
TMS320 family 1-2
characteristics 1-2
overview 1-2
TMS320C6000
internal memory configurations 3-2
peripherals 1-8
TMS320C6000 ('C6000) platform 1-1
TMS320C6000 Cache Architectures 4-2
TMS320C6000 cache architectures 3-2
TMS320C6201
cache architecture 3-2
data memory controller 3-7
internal memory configurations 3-2
TMS320C6201/C6701 block diagram 1-9, 1-10
TMS320C6202
cache architecture 3-2
data memory controller 3-7
data memory controller block diagram 3-7
external memory interface, figure 9-5
internal memory configuration 3-2
program and data memory 3-2
SDRAM interface 9-23
TMS320C6202 Block Diagram, figure 8-4
TMS320C6202 bootload 3-6
TMS320C6202 Memory Map Summary, table 10-6
TMS320C6202 program memory controller 3-1
TMS320C6202 program memory controller block
diagram 3-3
TMS320C6202 slave on the expansion bus 8-35
TMS320C6211, two level internal memory 4-1
TMS320C6211
block diagram 4-2
external memory interface, figure 9-6
interface signals 9-24
MTYPE field configurations 9-13
two–level internal memory 4-1
TMS320C6211 Block Diagram 6-2
figure 7-3
TMS320C6211 Boot Configuration Summary,
table 10-5
TMS320C6211 EMIF CE Space Control Register,
figure 9-12
Index-18
TMS320C6211 Internal Memory Block Diagram,
figure 4-3
TMS320C6211 Internal Memory Configurations,
table 4-2
TMS320C6211 Memory Map Summary, table 10-7
TMS320C6701
cache architecture 3-2
internal memory configuration 3-2
transfer, element 6-5
transfer complete code 6-13, 6-18
)transfer complete code (TCC 6-32
transfer complete code (TCC) field 6-34
Transfer Complete Code (TCC) to DMA Interrupt
Mapping, table 6-33
transfer complete interrupt 6-14
transfer parameter entry 6-12
transfer parameters 6-9, 6-13
transfer with frame synchronization 8-21
read transfer 5-2
transfers
2–dimensional 6-22
block 5-13
DMA 5-17
DMA examples 8-20
EDMA 6-17
EDMA linking 6-25
element 5-2, 5-23, 6-5
frame index 5-23
frame synchronized non–2D 6-21
linking EDMA 6-25
read 5-2
single frame example 8-20
transfer complete code 6-33
two dimensional 6-5
two–dimensional example 6-23
types 6-20
with frame synchronization 8-21
write 5-2
transmission, data 11-18
transmit control register (XCR) 11-14
transmit data companding format 11-51
transmit empty 11-45
figure 11-46
transmit empty avoided 11-46
transmit event 6-18
transmit interrupt (XINT) 11-22
transmit operation 11-34
transmit shift register (XSR) 11-4