Texas Instruments TMS320C6201 Reference Manual page 355

11.3.6.1 Frame Sync Ignore and Unexpected Frame Sync Pulses
Figure 11–20. Unexpected Frame Synchronization With (R/X)FIG = 0
CLK(R/X)
FS(R/X)
DR
A0
DX
A0
(R/X)SYNCERR
RFIG and XFIG are used to ignore unexpected frame sync pulses. Any frame
sync pulse is considered unexpected if it occurs one or more bit clocks earlier
than the programmed data delay from the end of the previous frame specified
by ((R/X)DATDLY). Setting the frame ignore bits to 1 causes the serial port to
ignore these unexpected frame sync signals.
In reception, if not ignored (RFIG = 0), an unexpected FSR pulse discards the
contents of RSR in favor of the incoming data. Therefore, if RFIG = 0, an unex-
pected frame synchronization pulse aborts the current data transfer, sets
RSYNCERR in the SPCR to 1, and begins the reception of a new data ele-
ment. When RFIG = 1, the unexpected frame sync pulses are ignored.
In transmission, if not ignored (XFIG = 0), an unexpected FSX pulse aborts the
ongoing transmission, sets the XSYNCERR bit in the SPCR to 1, and reiniti-
ates transmission of the current element that was aborted. When XFIG = 1,
unexpected frame sync signals are ignored.
Figure 11–20 shows that element B is interrupted by an unexpected frame sync
pulse when (R/X)FIG = 0. The reception of B is aborted (B is lost), and a new data
element (C) is received after the appropriate data delay. This condition causes a
receive synchronization error and thus sets the RSYNCERR bit. However, for
transmission, the transmission of B is aborted and the same data (B) is retrans-
mitted after the appropriate data delay. This condition is a transmit synchronization
error and thus sets the XSYNCERR bit. Synchronization errors are discussed in
sections 11.3.7.2 and 11.3.7.5.
Frame sync aborts current transfer
New data received
B7 B6 C7 C6
Current data retransmitted
B7 B6 B7 B6
Data Transmission and Reception
C5 C4 C3 C2
B5 B4 B3 B2
Multichannel Buffered Serial Ports
C1 C0 D7 D6
B1 B0 C7 C6
11-37