Figure 2-1 Signals Identified By Functional Group - Motorola DSP56309 User Manual

Signal/Connection Descriptions
Signal Groupings
PLL
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
CLKOUT
During
Reset
PINIT
EXTERNAL MEMORY INTERFACE
AA0ÐAA3/
RAS0ÐRAS3
Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0ÐPB15).
Signals with dual designations (e.g., HAS/HAS) have configurable polarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0ÐPC5), Port D GPIO signals
(PD0ÐPD5), and Port E GPIO signals (PE0ÐPE2), respectively.
3. TIO0ÐTIO2 can be configured as GPIO signals.
2-4
DSP56309
V
CCP
4
V
CCQL
3
V
CCQH
3
V
CCA
4
V
CCD
2
V
CCC
V
CCH
2
V
CCS
GND
P
GND
P1
4
GND
Q
4
GND
A
4
GND
D
2
GND
C
GND
H
2
GND
S
EXTAL
XTAL
PCAP
After
Reset
NMI
18
A0ÐA17
24
D0ÐD23
4
RD
WR
TA
BR
BG
BB
CAS
BCLK
BCLK

Figure 2-1 Signals Identified by Functional Group

DSP56309UM/D
fs
During Reset
MODA
MODB
MODC
MODD
RESET
Host Interface (H108)
Non-Multiplexed
Bus
8
H0ÐH7
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
Enhanced Synchronous Serial Interface (ESSI0)
3
SC00ÐSC02
SCK0
SRD0
STD0
Enhanced Synchronous Serial Interface (ESSI1)
3
SC10ÐSC12
SCK1
SRD1
STD1
Serial Communications Interface (SCI)
RXD
TXD
SCLK
3
Timers
TIO0
TIO1
TIO2
TCK
TDI
TDO
TMS
TRST
DE
After Reset
IRQA
IRQB
IRQC
IRQD
RESET
1
Multiplexed Port B
Bus GPIO
HAD0ÐHAD7 PB0ÐPB7
HAS/HAS PB8
HA8 PB9
HA9 PB10
HA10 PB13
Double DS
HRD/HRD PB11
HWR/HWR PB12
Double HR
HTRQ/HTRQ PB14
HRRQ/HRRQ PB15
Port C GPIO
PC0ÐPC2
PC3
PC4
PC5
Port D GPIO
PD0ÐPD2
PD3
PD4
PD5
2
Port E GPIO
PE0
PE1
PE2
GPIO
TIO0
TIO1
TIO2
AA0601
MOTOROLA