Power Signals - Motorola Digital DNA MSC8101 Technical Data Manual

Power Signals

1.2 Power Signals
V
V
V
V
GND
GND
GND
1-4
Table 1-1. Power and Ground Signal Inputs
Power Name
Internal Logic Power
DD
V dedicated for use with the device core. The voltage should be well-regulated and the
DD
input should be provided with an extremely low impedance path to the V
Input/Output Power
DDH
This source supplies power for the I/O buffers. The user must provide adequate external
decoupling capacitors.
System PLL Power
CCSYN
V dedicated for use with the system Phase Lock Loop (PLL). The voltage should be
CC
well-regulated and the input should be provided with an extremely low impedance path to the
V power rail.
CC
SC140 PLL Power
CCSYN1
V dedicated for use with the SC140 core PLL. The voltage should be well-regulated and
CC
the input should be provided with an extremely low impedance path to the V
System Ground
An isolated ground for the internal processing logic. This connection must be tied externally
to all chip ground connections, except GND
adequate external decoupling capacitors.
System PLL Ground
SYN
Ground dedicated for system PLL use. The connection should be provided with an extremely
low-impedance path to ground.
SC140 PLL Ground 1
SYN1
Ground dedicated for SC140 core PLL use. The connection should be provided with an
extremely low-impedance path to ground.
Description
DD
and GND . The user must provide
SYN SYN1
power rail.
power rail.
CC