Interrupt Table Memory Map; Interrupt Priority Level Bits - Motorola DSP56303 User Manual

Configuring Interrupts
The DSP56303 has a four-level interrupt priority structure. Each interrupt has two interrupt
priority level bits (IPL[1–0]) that determine its interrupt priority level. Level 0 is the lowest
priority; Level 3 is the highest-level priority and is non-maskable. Table 4-4 defines the IPL
bits.
IPL bits
xxL1 xxL0
0 0
0 1
1 0
1 1
The IPRC also selects the trigger mode of the external interrupts (
the IxL2 bit is 0, the interrupt mode is level-triggered. If the value is 1, the interrupt mode is
negative-edge-triggered.
4.4.2

Interrupt Table Memory Map

Each interrupt is allocated two instructions in the interrupt table, resulting in 128 table entries
for interrupt handling. Table 4-5 shows the table entry address for each interrupt source. The
DSP56303 initialization program loads the table entry for each interrupt serviced with two
interrupt servicing instructions. In the DSP56303, only some of the 128 vector addresses are
used for specific interrupt sources. The remaining interrupt vectors are reserved and can be
used for host (IPL = 3) or for host command interrupt (IPL = 2). Unused interrupt vector
NMI
locations can be used for program or data storage.
Interrupt
Priority Level
Starting Address
VBA:$00
VBA:$02
VBA:$04
VBA:$06
VBA:$08
VBA:$0A
VBA:$0C
4-20
Table 4-4. Interrupt Priority Level Bits
Interrupts Enabled
No
Yes
Yes
Yes
Table 4-5. Interrupt Sources
Interrupt
Range
3 Hardware RESET
3 Stack error
3 Illegal instruction
3 Debug request interrupt
3 Trap
3 Nonmaskable interrupt (NMI)
3 Reserved
DSP56303 User's Manual
Interrupts Masked
—
0
0, 1
0, 1, 2
IRQA
Interrupt Source
Interrupt Priority Level
0
1
2
3
– ). If the value of
IRQD