Table 4-11 Emi Sram Timing (Clock Cycles Per Word Transfer); Estm[3:0])— Bits 19–22 - Motorola DSP56009 User Manual

External Memory Interface
EMI Programming Model
Table 4-10 EMI DRAM Timing (clock cycles per word transfer) (Continued)
Addressing
Absolute
Absolute
Absolute
Absolute
Absolute
Absolute
Refresh Cycle
4.2.7.14 EMI SRAM Memory Timing (ESTM[3:0])— Bits 19–22
The read/write EMI SRAM Memory Timing (ESTM[3:0]) control bits select the EMI
SRAM Timing mode of operation. The ESTM[3:0] bits do not affect the timing of
DRAM mode accesses or of DRAM refresh cycles. See Section 4.8 EMI Timing for
more detailed information.
Note: ESTM[3:0] are set by hardware reset and software reset.

Table 4-11 EMI SRAM Timing (clock cycles per word transfer)

Word Length
8
8
12
16
12 or 16
20
24
20 or 24
Where ESTM is the value of the ESTM[3:0] bits, ranging from 0 to 15
4-20
Word Length Bus Width
12
16
12 or 16
20
24
20 or 24
—
Bus Width
4
8
4
4
8
4
4
8
DSP56009 User's Manual
EDTM = 1
(slow)
3 × 12 = 36
4
4 × 12 = 48
4
2 × 12 = 24
8
5 × 12 = 60
4
6 × 12 = 72
4
3 × 12 = 36
8
— 13
EDTM = 0 (fast)
3 × 8 = 24
4 × 8 = 32
2 × 8 = 16
5 × 8 = 40
6 × 8 = 48
3 × 8 = 24
9
Clock Cycles
2 × (4 + ESTM)
1 × (4 + ESTM)
3 × (4 + ESTM)
4 × (4 + ESTM)
2 × (4 + ESTM)
5 × (4 + ESTM)
6 × (4 + ESTM)
3 × (4 + ESTM)
MOTOROLA