Dma; Dsp56303 Block Diagram - Motorola DSP56303 User Manual

All internal buses on the DSP56300 family members are 24-bit buses. The program data bus
is also a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56303.
16
Triple
Interface
Timer
Address
Generation
Unit
Six-Channel
DMA Unit
Bootstrap
ROM
Internal
Data
Bus
Switch
EXTAL
Clock
Generator
XTAL
PLL
2
RESET
PINIT/NMI
Note: See Section 1.5.6, On-Chip Memory, on page 1-9 for memory size details.
1.7

DMA

The DMA block has the following features:
Six DMA channels supporting internal and external accesses
One-, two-, and three-dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
6 6 3
Host
SCI
ESSI
Interface Interface
HI08
Peripheral
Expansion Area
Program Program
Interrupt Decode
Controller Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1-1. DSP56303 Block Diagram
X Data
Program RAM
RAM
4096 24 bits
2048
(default)
bits
(default)
YAB
XAB
PAB
DAB
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Data ALU
Program
24 + 56
24
Address
Two 56-bit Accumulators
Generator
56-bit Barrel Shifter
Overview
Y Data
RAM
24 2048 24
bits
(default)
Memory
Expansion
Area
External
Address
Bus
Address
Switch
External
Bus
Interface
and
Control
I-Cache
Control
External
Data Bus
Switch
Power
Management
56-bit MAC
JTAG
OnCE
DMA
18
13
24
Data
5
DE
1-11