Figure 4-25 Sram Read/Write Timing; Timing Diagrams For Sram Addressing Modes - Motorola DSP56009 User Manual

External Memory Interface
EMI Timing
4.8.2

Timing Diagrams for SRAM Addressing Modes

When operating in the SRAM modes, the timing is selected by the ESTM bits in the
ECSR (see Section 4.2.7 on page 4-10). Figure 4-25 shows the timing diagrams for
read and write operations to/from SRAM memory. The cycle timing is shown at the
top; there are two clock cycles to set up the transfer and then from 1 to 16 cycles (as
determined by the ESTM bits), followed by the last cycle. This completes one
memory access. There can be from one to six memory accesses needed to transfer one
word, as shown in Table 4-11 on page 4-20.
One Nibble or Byte Access
CLK
Address
MCS
MRAS
MCAS
Read
MWR
MRD
Data In
Write
MWR
MRD
Data Out
4-64
1 2

Figure 4-25 SRAM Read/Write Timing

DSP56009 User's Manual
Repeat
ESTM + 1
last
Valid
Data
Valid
Data
1
AA0415
MOTOROLA