Endian Modes; Hi08 Read And Write Operations In Little Endian Mode - Motorola DSP56303 User Manual

Operation
6.4.5

Endian Modes

The Host Little Endian bit in the host-side Interface Control Register (ICR[5]=HLEND)
allows the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little
Endian mode (HLEND=1), a host transfer occurs as shown in Figure 6-4.
HTX/HRX Bit Number: 23
0
cc
aa bb
DSP side
Host side
High Byte
aa
Low Byte cc bb
(read/write last!)
$5 $6
Host bus address: $7
Host 32-bit
aa
xx cc bb
internal register
Figure 6-4. HI08 Read and Write Operations in Little Endian Mode
The host can transfer one byte at a time, so a 24-bit datum would be transferred using three
store (or load) byte operations, ensuring that the data byte at host bus address $7 is written last
since this causes the transfer of the data to the DSP-side HRX. However, the host bus
controller may be sophisticated enough that the host can transfer all bytes in a single operation
(instruction). For example, in the PowerPC MPC860 processor, the General-Purpose
Controller Module (GPCM) in the memory controller can be programmed so that the host can
execute a single read (load word, LDW) or write (store word, STW) instruction to the HI08
port and cause four byte transfers to occur on the host bus. The 32-bit datum transfer shown in
Figure 6-4 has byte data xx written to HI08 address $4, byte aa to address $5, byte bb to
address $6 and byte cc to address $7 (this assumes the 24-bit datum is contained in the lower
24 bits of the host's 32-bit data register as shown).
6-11
Host Interface (HI08)