Table 4-10 Emi Dram Timing (Clock Cycles Per Word Transfer); Emi Busy (Ebsy)—Bit 15 - Motorola DSP56009 User Manual

4.2.7.11 EMI Busy (EBSY)—Bit 15
The EMI Busy (EBSY) read-only status bit indicates the EMI state. EBSY is set when
the EMI is busy transferring data or when there is a pending transfer request. EBSY is
cleared when no transfers currently are being done and no requests are pending.
Note: EBSY is cleared by hardware reset, software reset, individual reset, and while
the DSP is in the Stop state.
4.2.7.12 EMI Read Trigger Select (ERTS)—Bit 17
The read/write EMI Read Trigger Select (ERTS) control bit selects the trigger event
for read operations. When ERTS is cleared, read operations are triggered by a write
to the EOR. When ERTS is set, read operations are triggered by reading the EDRR.
Note: ERTS is cleared by hardware reset and software reset.
4.2.7.13 EMI DRAM Memory Timing (EDTM)—Bit 18
The read/write EMI DRAM Memory Timing (EDTM) control bit selects the EMI
DRAM Timing mode of operation. When EDTM is set, EMI DRAM mode accesses
and DRAM refresh cycles operate in the Slow Timing mode. When EDTM is cleared,
EMI DRAM mode accesses and DRAM refresh cycles operate in the Fast Timing
mode. The EDTM bit does not affect the timing of SRAM accesses. See Section 4.8
EMI Timing for more detailed information.
Note: EDTM is set by hardware reset and software reset.

Table 4-10 EMI DRAM Timing (clock cycles per word transfer)

Addressing
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Absolute
Absolute
MOTOROLA
Word Length Bus Width
8
8
12
16
12 or 16
20
24
20 or 24
8
8
DSP56009 User's Manual
External Memory Interface
EMI Programming Model
EDTM = 1
(slow)
4 16
8 12
4 20
4 24
8 16
4 28
4 32
8 20
2 × 12 = 24
4
1 × 12 = 12
8
EDTM = 0 (fast)
11
8
14
17
11
20
23
14
2 × 8 = 16
1 × 8 = 8
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