Cra Prescaler Range (Psr) Bit 15; Ssi Control Register B (Crb) - Motorola DSP56156 Manual

These bits control the Word Length Divider shown in the SSI Clock Generator. The WL
control bits also controls the frame sync pulse length when FSL=0.
When WL1-WL0= 01, the received logarithmic byte is automatically expanded to a 13 or
14 bit word in the RX register. The result is left justified in the RX register. When transmit-
ting, a 16-bit left justified word written to the TX register will be truncated to 13/14 bits be-
fore logarithmic compression. The A/MU bit 3 of CRB will select which compression law,
A or MU, is used.
Note: When the A/MU law is enabled, the data to be transmitted should be written to the
TX register before the second to last clock of the previous slot. Otherwise a trans-
mit underrun error occurs.
8.11.4

CRA Prescaler Range (PSR) Bit 15

The Prescaler Range controls a fixed divide-by-8 prescaler in series with the variable
prescaler. It is used to extend the range of the prescaler for those cases where a slower
bit clock is desired. When PSR is cleared the fixed prescaler is bypassed. When PSR is
set the fixed divide-by-8 prescaler is operational. This allows a 128kHz master clock to be
generated for Motorola codecs. The maximum internally generated bit clock frequency is
Fosc/4 and the minimum internally generated bit clock frequency is Fosc/(4*8*256).
8.12

SSI CONTROL REGISTER B (CRB)

The SSI Control Register B is one of two, 16-bit read/write control registers used to direct
the operation of the SSI. CRB controls the direction of the bit clock pin (SCK) and the func-
tion of the SC1x and SC0x pins. Interrupt enable bits for each data register interrupt are
provided in this control register. SSI operating modes are also selected in this register.
The DSP reset clears all CRB bits. SSIx reset and STOP reset do not affect the CRB bits.
The SSI Control Register B bits are described in the following paragraphs.
MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)

SSI CONTROL REGISTER B (CRB)

Table 8-3 SSI Data Word Lengths
WL1 WL0 Number of bits/word
0 0
0 1 8 with log exp/comp
1 0
1 1
8
12
16
8 - 15