Hsr Reserved-Bits 5 And 6; Hsr Dma Status (Dma)-Bit 7; Hi Receive Data Register (Horx); Figure 4-9 Hi Flag Operation - Motorola DSP56012 User Manual

Parallel Host Interface
Host Interface (HI)
7
Host
$0
INIT
7
DSP56012 X:$FFE9
DMA
7
Host
$2
HOREQ
7
DSP56012 X:$FFE8
0
4.4.4.2.6 HSR Reserved—Bits 5 and 6
These status bits are reserved for future revisions and read as 0s during DSP read
operations.
4.4.4.2.7 HSR DMA Status (DMA)—Bit 7
The DMA bit indicates that the host processor has enabled the DMA mode of the HI
by setting HM1 or HM0 to 1. When the DMA bit is 0, it indicates that the DMA mode
is disabled by the HM0 and HM1 bits (in the ICR) and that no DMA operations are
pending. When the DMA bit is set, the DMA mode has been enabled if one or more
of the host mode bits have been set. The channel not in use can be used for polling or
interrupt operation by the DSP.
Note: Hardware reset, software reset, individual reset, and Stop clear the DMA bit.
4.4.4.3

HI Receive Data Register (HORX)

The HI Receive data register (HORX) is used for host-to-DSP data transfers. The
HORX register is viewed as a 24-bit read-only register by the DSP CPU. The HORX
register is loaded with 24-bit data from the Transmit data registers (TXH:TXM:TXL)
on the host processor side when both the host-side Transmit Data register Empty
4-18
Host to DSP56012 Status Flags
HM1 HM0 HF1 HF0
0 0 HF1 HF0
DSP56012 to Host Status Flags
DMA 0 HF3 HF2
0 0 HF3 HF2

Figure 4-9 HI Flag Operation

DSP56012 User's Manual
0
Interrupt Control Register
(ICR)
0 TREQ RREQ
(Read/write)
0
Host Status Register
(HSR)
HCP HTDE HRDF
(Read Only)
0
Interrupt Status Register
(ISR)
TRDY TXDE RXDF
(Read Only)
0
Host Control Register
(HCR)
HCIE HTIE HRIE
(Read/write)
AA0316
MOTOROLA