Figure 4-4 Pll Control (Pctl) Register; Pll Control Register; Device Identification Register (Idr) - Motorola DSP56309 User Manual

Core Configuration

PLL Control Register

4.7 PLL CONTROL REGISTER
The PLL Control (PCTL) register is an X-I/O mapped, 24-bit, read/write register that
directs the operation of the on-chip PLL. The PCTL control bits are shown in Figure 4-4.
Refer to the DSP56300
11 10
MF11 MF10
23 22
PD3 PD2
4.7.1 PCTL PLL Multiplication Factor Bits 0Ð11
The multiplication factor bits (MF[11:0]) define the Multiplication Factor (MF) that is
applied to the PLL input frequency. The MF bits are cleared during a DSP56309
hardware reset, which corresponds to an MF of one.
4.7.2 PCTL XTAL Disable Bit (XTLD) Bit 16
The XTAL disable bit (XTLD) controls the on-chip crystal oscillator XTAL output. The
XTLD bit is cleared during a DSP56309 hardware reset, which means that the XTAL
output signal is active, permitting normal operation of the crystal oscillator.
4.7.3 PCTL Predivider Factor Bits (PD0ÐPD3) Bits 20Ð23
The predivider factor bits (PD0ÐPD3) define the predivision factor (PDF) to be applied to
the PLL input frequency. The PD0ÐPD3 bits are cleared during a DSP56309 hardware
reset, which corresponds to a PDF of one.
4.8

DEVICE IDENTIFICATION REGISTER (IDR)

The device identification register (IDR) is a 24-bit, read-only factory programmed
register that identifies DSP56300 family members. It specifies the derivative number and
4-18
for a full description of the PCTL.
Family Manual
9 8 7 6
MF9 MF8 MF7 MF6
21 20 19 18
PD1 PD0 COD PEN

Figure 4-4 PLL Control (PCTL) Register

DSP56309UM/D
5 4 3
MF5 MF4 MF3 MF2
17 16 15 14
PSTP XTLD XTLR DF2
2 1 0
MF1 MF0
13 12
DF1 DF0
AA0852
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