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Parallel Host Interface
Host Interface (HI)
7
X:$FFE8
0
0
7
DMA
X:$FFE9
0
(0)
23
Receive
X:$FFEB
High Byte
Transmit
X:$FFEB
High Byte
7
Note:
1.
The numbers in parentheses are reset initialization values.
Figure 4-8 HI Programming Model–DSP Viewpoint
The following paragraphs describe the purpose and operation of each bit in each
register of the HI that is visible to the DSP. The effects of the different types of reset
on these registers are shown. A brief discussion of interrupts and operation of the
DSP side of the HI complete the programming model from the DSP viewpoint. The
programming model from the host viewpoint begins at Section 4.4.5.1
Programming Model—Host Processor Viewpoint.
4.4.4.1
HI Control Register (HCR)
The HI Control Register (HCR) is an 8-bit read/write control register used by the
DSP to control the host interrupts and flags. The HCR cannot be accessed by the host
processor. It occupies the low-order byte of the internal data bus; the high-order
4-14
HF3
HF2
HCIE
0
(0)
(0)
(0)
Host Flags
Host Flag 1
Host Flag 0
HF1
HF0
HCP
0
(0)
(0)
(0)
16 15
8 7
Receive
Middle Byte
Transmit
Middle Byte
0 7
0 7
DSP56012 User's Manual
DSP CPU Flags
Host Flag 3
Host Flag 2
0
Host Control Register (HCR)
HTIE
HRIE
(Read/Write)
(0)
(0)
Interrupt Enables
Host Receive
Host Transmit
Host Command
0
HTDE
HRDF
Host Status Register (HSR)
(Read Only)
(1)
(0)
Host Receive Data Full
Host Transmit Data Empty
Host Command Pending
0
Receive
Host Receive Data
Low Byte
Register (HORX) (Read Only)
Transmit
Host Transmit Data
Low Byte
Register (HOTX) (Write Only
0
)
AA0315k
MOTOROLA
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