Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 89

Table 2-7. DMA Channel Registers: Controls, Parameters,
and Buffers (Cont'd)
DMA Control Registers
Channel
Number
12 SPCTL7
13 SPCTL7
14 SPCTL6
15 SPCTL6
16 IDP_CTL
17 IDP_CTL
18 IDP_CTL
19 IDP_CTL
20 IDP_CTL
21 IDP_CTL
22 IDP_CTL
ADSP-21368 SHARC Processor Hardware Reference
Parameter Registers
IISP7A, IM7P5A, CSP7A,
CPSP7A
IISP7B, IMSP7B, CSP7B,
CPSP7B
IISP6A, IMSP6A, CSP6A,
CPSP6A
IISP6B, IMSP6B, CSP6B,
CPSP6B
IDP_DMA_I0,
IDP_DMA_M0,
IDP_DMA_C0
IDP_DMA_I1,
IDP_DMA_M1,
IDP_DMA_C1
IDP_DMA_I2,
IDP_DMA_M2,
IDP_DMA_C2
IDP_DMA_I3,
IDP_DMA_M3,
IDP_DMA_C3
IDP_DMA_I4,
IDP_DMA_M4,
IDP_DMA_C4
IDP_DMA_I5,
IDP_DMA_M5,
IDP_DMA_C5
IDP_DMA_I6,
IDP_DMA_M6,
IDP_DMA_C6
I/O Processor
Buffer Registers Description
RXSP7A, Serial Port
TXSP7A 7A Data
RXSP7B, Serial Port
TXSP7B 7B Data
RXSP6A, Serial Port
TXSP6A 6A Data
RXSP6B, Serial Port
TXSP6B 6B Data
IDP_FIFO DAI IDP
Channel 0
IDP_FIFO DAI IDP
Channel 1
IDP_FIFO DAI IDP
Channel 2
IDP_FIFO DAI IDP
Channel 3
IDP_FIFO DAI IDP
Channel 4
IDP_FIFO DAI IDP
Channel 5
IDP_FIFO DAI IDP
Channel 6
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