Dma Transfer Notes - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

DMA Transfer Notes

The following items provide general information about DMA transfers.
• A DMA can be interrupted by changing the
IDP_CTL0
the
IDP_ENABLE
bit (= 0) does not affect the data in the FIFO, it only stops DMA
transfers. If the IDP remains enabled, an interrupted DMA can be
resumed by setting the
IDP_ENABLE
FIFO starts accepting new data.
• Using DMA transfers overrides the mechanism that is used for
interrupt-driven manual reads from the FIFO. When the
IDP_DMA_EN
register are set, the eighth interrupt in the
DAI_IRPTL_H
interrupt detects the condition that the number of data available in
FIFO is more than the number set in the
the
IDP_CTL0
• At the end of the DMA transfer for individual channels, interrupts
are generated. These interrupts are generated after the last DMA
data from a particular channel has been transferred to memory.
These interrupts are mapped to the
to the
IDP_DMA0_INT
DAI_IRPTL_H
set (= 1). These bits are ORed and reflected in high-level interrupts
sent to the core.
• If the combined data rate from the channels is more than the DMA
can service, a FIFO overflow occurs. This condition is reflected for
each channel by the individual overflow bits (
DAI_STAT
writing to the
ADSP-21368 SHARC Processor Hardware Reference
register. None of the other control settings (except for
bit) should be changed. Clearing the
IDP_DMA_EN
bit flushes the data in the FIFO. If the bit is set again,
bit and at least one
registers (
IDP_FIFO_GTN_INT
register).
bit (bit 10) in the
registers and they generate interrupts when they are
register. These are W1C bits that must be cleared by
bit (bit 6 of the
IDP_CLROVR
Input Data Port
IDP_DMA_EN
bit again. But resetting the
bit in the
IDP_DMA_ENx
DAI_IRPTL_L
) is not generated. This
IDP_NSET
IDP_DMA7_INT
DAI_IRPTL_L
SRU_OVF
IDP_CTL0
bit in the
IDP_DMA_EN
IDP_CTL1
or
bits (bits 3–0 of
bit (bit 17), and
or
) in the
register).
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