Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 547

PERIPHERAL
INTERFACE
IRQ
Figure 12-1. TWI Block Diagram
The transmit shift register serially shifts its data out externally off chip.
The output can be controlled to generate acknowledgements or it can be
manually overwritten.
The receive shift register receives its data serially from off chip. The
receive shift register is 1 byte wide and data received can either be trans-
ferred to the FIFO buffer or used in an address comparison.
The address compare block supports address comparison in the event the
TWI controller module is accessed as a slave.
The prescaler block must be programmed to generate a 10 MHz time ref-
erence relative to the peripheral clock. This time base is used for filtering
data and timing events specified by the electrical parameters in the data
sheet (see the I
generation.
ADSP-21368 SHARC Processor Hardware Reference
FIFO
REGISTERS
2
C bus specification from Philips), as well as for
Two Wire Interface Controller
TRANSMIT SHIFT
REGISTER
ARBITRATION
RECEIVE SHIFT
REGISTER
ADDRESS COMPARE
PRESCALER
CLOCK GENERATION
SDA
SCL
clock
SCL
12-3