Ping-Pong Dma - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

FIFO to Memory Data Transfer
6. Enable DMA, IDP, and PDAP (if required) by setting each of the
following bits = 1:
•
IDP_DMA_EN
•
IDP_DMA_ENx
the selected channel
•
IDP_PDAP_EN
•
IDP_ENx
•
IDP_ENABLE
A DAI interrupt is generated at the end of each DMA.
7. After the DMA completes, connect the clock and frame sync sig-
nals to 0.

Ping-Pong DMA

This mode gets activated when the
and the
IDP_PINGx
channel.
In ping-pong DMA, the parameters have two memory index values (index
A and index B), one count value and one modifier value. The DMA starts
the transfer with the memory indexed by A. When the transfer is com-
pleted as per the value in the count register, the DMA restarts with the
memory location indexed by B. The DMA restarts with index A after the
transfer to memory with index B is completed as per the count value. This
repeats until the DMA is stopped by resetting the
bits.
IDP_PINGx
7-22
bit (bit 5 of the
bits in
IDP_CTL1
bit (bit 31 in
of to enable the selected channel
IDP_CTL1
bit (bit 7 in the
IDP_DMA_EN
bit in the
IDP_CTL1
ADSP-21368 SHARC Processor Hardware Reference
register)
IDP_CTL0
register to enable the DMA of
register)
IDP_PP_CTL
register)
IDP_CTL0
bit of the
IDP_CTL0
register are set for a particular
IDP_DMA_EN
register
or