Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 118

External Memory Interface
ADSP-213xx
24
Sequencer
Packing
Unit
Figure 3-3. Logical Versus Physical Addresses
The address range of external memory (asynchronous memory) is shown
in Table 3-1. External bank 0 can be used to execute instructions.
Table 3-1. External Memory Address Space for Non SDRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Table 3-2 shows the addressable range for SDRAM memory space. Bank 0
can be used for executing instructions. Note that the external memory
bank addresses shown are for normal word accesses.
The actual throughput execution from external SDRAM is dependent on
the configuration of the SDRAM. The SDRAM can be programmed to
run at a number of different frequency ratios with respect to the core
clock, the fastest being half of the core clock (or the same as the peripheral
clock). The core and SDRAM controller have been enhanced so that
3-10
"Logical
Address"
Address
48
Data
Size in words Address Range
14M 0x0020 0000 – 0x00FF FFFF
16M 0x0400 0000 – 0x04FF FFFF
16M 0x0800 0000 – 0x08FF FFFF
16M 0x0C00 0000 – 0x0CFF FFFF
ADSP-21368 SHARC Processor Hardware Reference
Address" on
External
address bus
Port
Address
Translator
"Instruction Data"
on data bus
"Physical External
Memory
Bank 0
24
16/32 bit*
*32-bit on the ADSP-21371 and
16-bit on the ADSP-21375.