Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 622

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Table of Contents

Clock Derivation

(see data sheet)

BOOT CLKCFG[]->PLLM[] CFG

1. CLKOUT is muxed with RESETOUT. After reset, RESETOUT is selected . CLKOUT is selected by setting bit 12 in the PMCTL register.

2.The PLL ratio is controlled by the states of the CLKCFG[1:0] pins at reset and can be modified in software throu gh the

PLLM and PLLDx bits in the PMCTL register.

3.To place the PLL in bypass mode, set bit 15 in the PMCTL register. (CCLK = PLLICLK when set.)

4. Programs can interrupt the internal clock source to each of the following peripherals: timer, SPI, SPORTs, and parallel port.

These internal clock sources are disabled at reset and are enabled and left enabled after each peripheral is enabled.

Note that these peripherals DO NOT RUN at the core clock freq uency. For more information please see the respective peripheral

chapters in the ADSP-2136x SHARC Processor Hardware Reference.

5. Please refer to the processor specific data sheets for maximum CLKIN and crystal source specifications.

Figure 14-8. Core Clock and System Clock Relationship to CLKIN

Table 14-5. CLKOUT and CCLK Clock Generation Operation

Requirements

P LL BYP AS S; Reserved

4096 x CLKIN

CLKOUTEN[12]

ADSP-21368 SHARC Processor Hardware Reference

160 MHz < VCO_OUT < 800 MHz

Local Clock Out

PLL Input Clock

SDRATIO[20..18]

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