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SRU2_INPUT1
(0x1C01)
Reserved
TWI_SCLK_I
TWI Serial Clock Input
UART1_RX_I
UART 1 Receiver Input
UART0_RX_I
UART 0 Receiver Input
Figure 4-42. SRU2_INPUT1 Register
SRU2_INPUT2
(0x1C02)
Reserved
FLAG6_I
Flag 6 Input
FLAG4_I
Flag 4 Input
TIMER2_I
Timer 2 Input
Figure 4-43. SRU2_INPUT2 Register
ADSP-21368 SHARC Processor Hardware Reference
Digital Audio/Digital Peripheral Interfaces
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
1
1
0
1
15 14 13 12 11 10
9
8
0
0
1
0
1
1
0
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Reset = 0x1AC02C00
0
UART1_RX_I
UART 1 Receiver Input
TWI_SDATA_I
TWI Serial Data Input
0
0
SPIB_DS_I
SPIB Device Select Input
SPIB_CLK_I
SPI B Clock Input
Reset = 0x00000000
0
FLAG4_I
Flag 4 Input
FLAG5_I
Flag 5 Input
0
0
TIMER0_I
Timer 0 Input
TIMER1_I
Timer 1 Input
4-53
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