Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 324

Data Word Formats
Reserved
SP7 FSERR Int Status
SP7 DERRB Int Status
SP7 DERRA Int Status
SP6 DERRB Int Status
SP6 DERRA Int Status
SP5 DERRB Int Status
SP5 DERRA Int Status
SP4 DERRB Int Status
SP4 DERRA Int Status
Figure 5-9. SPERRSTAT Register
The value of
SLEN
= serial word length – 1
SLEN
Do not set the
right-justified in the receive and transmit buffers, residing in the least sig-
nificant (LSB) bit positions.
Although the word lengths can be 3 to 32 bits, transmitting or receiving
words smaller than 7 bits at one-quarter the full clock rate of the SPORT
may cause incorrect operation when DMA chaining is enabled. Chaining
disables the processor's internal I/O bus for several cycles while the new
transfer control block (TCB) parameters are being loaded. Receive data
may be lost (for example, overwritten) during this period.
5-44
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
is:
value to 0 or 1. Words smaller than 32 bits are
SLEN
ADSP-21368 SHARC Processor Hardware Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0
0
SP0 FSERR Int Status
SP1 FSERR Int Status
SP2 FSERR Int Status
SP3 FSERR Int Status
SP4 FSERR Int Status
SP5 FSERR Int Status
SP6 FSERR Int Status
0
0
SP0 DERRA Int Status
SP0 DERRB Int Status
SP1 DERRA Int Status
SP1 DERRB Int Status
SP2 DERRA Int Status
SP2 DERRB Int Status
SP3 DERRA Int Status
SP3 DERRB Int Status