Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 146

SDRAM Controller
PLLD Bit Setting
00
01
10
11
SDCKR Bit Setting
000
001
010
011
100
3. Enable the new divisors by setting the
register). Do not set this bit at the same time as the
15 of the
Register" on page 14-14
The new divisor ratios are picked up on the fly and the clocks
smoothly transition to their new values within 14 core clock (
cycles.
The core clock frequency is:
× (PLL multiplier ÷ clock divider) where:
=
CCLK CLKIN
PLL multiplier = PLLM (1–64) and the PLL divider = 1, 2, 4 or 8.
The frequency is
SDCLK
If either the PLL divider or the
it may take up to 14
3-38
Clock Ratio
CCLK divider of 1
CCLK divider of 2
CCLK divider of 4
CCLK divider of 8
Clock Ratio
SDCLK divider of 2
SDCLK divider of 2.5
SDCLK divider of 3
SDCLK divider of 3.5
SDCLK divider of 4
register) is set. See
PMCTL
for more information.
=
SDCLK CCLK
SDCLK
cycles for all the clocks to get the new value.
CCLK
ADSP-21368 SHARC Processor Hardware Reference
bit (bit 9 in the
DIVEN
"Power Management Control
÷
.
SDRATIO
to ratio (or both) are changed,
CCLK
PMCTL
bit (bit
PLLBP
)
CCLK