Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 90

Setting Up DMA Parameter Registers
Table 2-7. DMA Channel Registers: Controls, Parameters,
and Buffers (Cont'd)
DMA Control Registers
Channel
Number
23 IDP_CTL
24 SPICTL
25 SPICTLB
26 MTMCTL
27 MTMCTL
28 AMICTL
29 AMICTL
30 RXCTL_UAC0
31 RXCTL_UAC1
2-34
Parameter Registers
IDP_DMA_I7,
IDP_DMA_M7,
IDP_DMA_C7
IISPI, IMSPI, CSPI, CPSPI
IISPIB, IMSPIB, CSPIB,
CPSPIB
IIMTMW
IMMTMW,
CMTMW
IIMTMR,
IMMTMR,
CMTMR
EIEP0, EMEP0, ECEP0,
IIEP0, IMEP0, ICEP0,
CEP0, CPEP0, EBEP0,
TPEP0, ELEP0
EIEP1, EMEP1, ECEP1,
IIEP1, IMEP1, ICEP1,
CEP1, CPEP1, EBEP1,
TPEP1, ELEP1
RXI_UAC0, RXM_UAC0,
RXC_UAC0, RXCP_UAC0,
RXSTAT_UAC0
RXI_UAC1, RXM_UAC1,
RXC_UAC1, RXCP_UAC1,
RXSTAT_UAC1
ADSP-21368 SHARC Processor Hardware Reference
Buffer Registers Description
IDP_FIFO DAI IDP
Channel 7
RXSPI, TXSPI SPI Data
RXSPIB, SPI B Data
TXSPIB
N/A MTM Write
Channel
N/A MTM Read
Channel
DFEP0, TFEP0 External
Port
Channel 0
DFEP1, TFEP1 External
Port
Channel 1
RBR0, UART0 Rx
RBRSH_UAC0
RBR1, UART1 Rx
RBRSH_UAC1