Bus Mastership Time-Out - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Table 3-31. Rotating Priority Arbitration Example (Cont'd)
Cycle Number
4
3
5
1 The following symbols appear in these cells: 1-3 = assigned priority, M = bus mastership (in that
cycle), BR = requesting bus mastership with BRx
2 Initial priority assignments
3 Final priority assignments

Bus Mastership Time-out

In either the fixed or rotating priority scheme, systems may need to limit
how long a bus master can retain the bus. This is accomplished by forcing
the bus master to deassert its
cycles and giving the other processors a chance to acquire bus mastership.
To set up a bus master time-out, a program must load the bus time-out
maximum (
BMAX
mum number of
bus mastership. This equation is shown below.
= (maximum number of bus mastership
BMAX
The minimum value for
tership for four
bus master time-out function, set
Each time a processor acquires bus mastership, its bus time-out counter
( register, address = 0x180E) is loaded with the value in
BCNT
is then decremented in every
BCNT
forms a read or write over the bus and any other (slave) processors are
requesting the bus. Any time the bus master deasserts its
reloaded from
ADSP-21368 SHARC Processor Hardware Reference
Hardwired Processor IDs and Priority
ID1 ID2
3-BR M
1-BR 2
BRx
register, address = 0x180D,
cycles (minus 2) that allows the processor to retain
CLKIN
is 2, which lets the processor retain bus mas-
BMAX
cycles. Setting
CLKIN
.
BMAX
1
ID3
1
3
line after a specified number of
Figure
CLKIN
=1 is not allowed. To disable the
BMAX
=0.
BMAX
cycle in which the master per-
CLKIN
External Port
ID4
2-BR
M
CLKIN
3-17) with the maxi-
cycles) – 2
. The
BMAX
line,
BRx BCNT
3-87
is