Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 442

FIFO to Memory Data Transfer
•
IDP_Pxx_PDAPMASK
the input mask, if the PDAP is used.
see "Parallel Data Acquisition Port Control Register
(IDP_PP_CTL)" on page A-74.
•
IDP_PORT_SELECT
input from the DAI pins or the data pins, if the PDAP is
used.
•
IDP_PDAP_CLKEDGE
specify if data is latched on the rising or falling clock edge, if
the PDAP is used.
5. Connect all of the inputs to the IDP by writing to the
and
SRU_DAT5
ters. Keep the clock and frame sync of the ports connected to low
when data transfer is not intended.
6. Enable DMA, IDP, and PDAP (if required) by setting each of the
following bits = 1:
•
IDP_DMA_EN
•
IDP_PINGx
DMA of the selected channel
•
IDP_PDAP_EN
•
IDP_ENx
•
IDP_ENABLE
7. After the DMA completes, connect the clock and frame sync sig-
nals to 0.
An interrupt is generated after every ping and pong DMA transfer
(when the count = 0).
7-24
bits in the
bits in the
bit (bit 29) in the
, and
SRU_FS2 SRU_FS3
bit (bit 5 of the
bit in
IDP_CTL1
bit (bit 31 in
of to enable the selected channel
IDP_CTL1
bit (bit 7 in the
ADSP-21368 SHARC Processor Hardware Reference
register to specify
IDP_PP_CTL
For more information,
register to specify
IDP_PP_CTL
IDP_PP_CTL
, and
SRU_CLK2 SRU_CLK3
register)
IDP_CTL0
register to enable the ping-pong
register)
IDP_PP_CTL
register)
IDP_CTL0
register to
SRU_DAT4
regis-