Enabling Sport Master Mode (Mstr); Selecting Transmit And Receive Channel Order (Frfs); Selecting Frame Sync Options (Difs) - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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Enabling SPORT Master Mode (MSTR)

The SPORTs transmit and receive channels can be configured for master

or slave mode. In master mode, the processor generates the word select

and serial clock signals for the transmitter or receiver. In slave mode, an

external source generates the word select and serial clock signals for the

transmitter or receiver. When

external word select and clock source and the SPORT transmitter or

receiver is a slave. When

internal clock for word select and clock source and the SPORT transmit-

ter or receiver is the master. For more information, see

Internal Serial Clock and Frame Sync Rates" on page

In master and slave modes, programs can configure which I

each SPORT channel transmits or receives first. By default, the SPORT

channels transmit and receive on the right I

S channels are time-duplexed data channels.

To select the channel order, set the

the left channel first, or clear the

the right channel first.

bit selects whether the serial port uses the data independent

frame sync or the data dependant frame sync. Normally, the internally

generated frame sync signal is output only when the transmit buffer has

data ready to transmit for the transmitter and when the receive buffer is

not full for the receiver. The data-independent frame sync (DIFS) mode

allows the continuous generation of the

data in the transmit register or the receive buffer.

ADSP-21368 SHARC Processor Hardware Reference

is cleared (=0), the processor uses an

is set (=1), the processor uses the processor's

bit (= 1) to transmit or receive on

bit (= 0) to transmit or receive on

Serial Ports

"Setting the

S channel that

S channel first. The left and

signal, with or without new