Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 712

Serial Peripheral Interface Registers
Table A-15. SPIDMAC, SPIDMACB Register Bit Descriptions (Cont'd)
Bit Name
13–12 SPISx
14 SPIERRS
15 SPIDMAS
16 SPICHS
31–17 Reserved
SPI DMA Start Address Registers (IISPI, IISPIB)
The reset values for these registers are undefined. These 19-bit read-write
SPI registers contain the start address of the buffer in memory. Their
addresses are 0x1080 (for
SPI DMA Address Modify Registers (IMSPI, IMSPIB)
The reset values for these registers are undefined. These 16-bit, read-write
SPI registers contain the address modifier. Their addresses are 0x1081 (for
) and 0x2881 (for
IMSPI
SPI DMA Word Count Registers (CSPI, CSPIB)
The reset values for these registers are undefined. These 16-bit, read-write
SPI registers contain the number of words to be transferred. Their
addresses are 0x1082 (for
A-64
Description
DMA FIFO Status.
00 = FIFO empty
11 = FIFO full
10 = FIFO partially full
01 = Reserved
DMA Error Status.
0 = Successful DMA transfer
1 = Errors during DMA transfer
DMA Transfer Status.
0 = DMA idle
1 = DMA in progress
DMA Chain Loading Status.
0 = Chain idle
1 = Chain loading in progress
) and 0x2880 (for
IISPI
).
IMSPIB
) and 0x2882 (for
CSPI
ADSP-21368 SHARC Processor Hardware Reference
).
IISPIB
).
CSPIB