Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 705

Table A-11. SPISTAT Register Bit Descriptions
Bit Name
0 SPIF
1 MME
2 TUNF
3 TXS
4 ROVF
5 RXS
6 TXCOL
7 SPIFE
31-8 Reserved
ADSP-21368 SHARC Processor Hardware Reference
Description
SPI Transmit or Receive Transfer Complete. SPIF is set when an
SPI single-word transfer is complete.
Multimaster Error or Mode-Fault Error. MME is set in a master
device when some other device tries to become the master.
Transmission Error. TUNF is set when transmission occurred with
no new data in TXSPI register.
Transmit Data Buffer Status. TXSPI data buffer status.
0 = Empty
1 = Full
Reception Error. ROVF is set when data is received with receive
buffer full
Receive Data Buffer Status.
0 = Empty
1 = Full
Transmit Collision Error. When TXCOL is set, it is possible that
corrupt data was transmitted.
External Transaction Complete. Set (= 1) when the SPI transaction
is complete on the external interface.
Register Reference
A-57